In the context of CMOS scaling, it is established that below 7-nm CMOS generation, i.e. sub N7, the standard planar/FinFET architecture may switch to a vertical type of integration in order to continue scaling. Furthermore, electrostatic control may be improved. One solution is to develop an architecture based on gate-all-around (GAA) vertical nanowires. Furthermore, in order to boost the drive current performances of the device, a high mobility channel such as a III-V based channel may be used.
Based on the scaling predictions for N5 CMOS generation, the channel diameter may be smaller than 10 nm and more than one channel may be used in the device to increase drive current capabilities. Also, the channels may be as defect-free as possible in order to assure good electrical performances. Additionally, in the vertical architecture, the source/drain regions for contacts may be highly doped (n-type or p-type), e.g., in-situ, which could cause dopant diffusion in the channel which would degrade the carrier mobility. These issues represent key engineering challenges.
US Patent application 2013/0240983A1 discloses a process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, including a plurality of elementary transistors, each elementary transistor comprising a source electrode and a drain electrode each positioned at one end of a vertical nanowire and connected by a channel, with a gate electrode surrounding each vertical nanowire. US Patent application 2013/0240983A1 discloses that these nanowires may be made from a group IV or group III-V materials and that these nanowires may be made top-down (e.g. via etching). Alternatively, they may be made bottom-up (e.g. growth). It does not disclose a way to grow nanowires and therefore may not address the problem of how to grow nanowire-based channels with high crystalline quality. As having a low defect density vertical nanowire may be helpful for device performance (e.g., for nanowire-based channels of FETs), there is still a need in the art for reducing the amount of defects in vertical nanowires and for methods to obtain the same.